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SI9750
Vishay Siliconix
Hot Swap SI9750
In-Rush Current Limit MOSFET Driver
FEATURES
* 2.9- to 13-V Input Operating Range * Microprocessor RESET * Integrated High-Side Driver for N-Channel MOSFET * Programmable di/dt Current
DESCRIPTION
The SI9750 current limit MOSFET interface IC is designed to operate between a power source and a load using a low onresistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The SI9750 current limiter prevents source and load transients during hot swap and power-on with programmable dv/dt and di/dt. Both turn-on and steady-state current limits can be individually programmed, providing protection against short circuits. Power on RESET and logic controls allow complete microprocessor interfacing. The RESET function of the SI9750 is industry-standard with full programmability. The SI9750 is available in a 16-pin SOIC package and is rated over the commercial temperature range (0 to 70C).
FUNCTIONAL BLOCK DIAGRAM
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SI9750
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to Ground VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Boost Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 V Inputs/Outputs (except Gate, Boost and VRST) . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 V VRST Input Current (0 < VRST < 15 V) . . . . . . . . . . . . . . . . . . . .20 mA Inputs/Outputs Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA RESET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 mA STATUS Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 mA
* Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (package)a 16-Pin SOICb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (JA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/C above 25C.
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Supply
Quiescent Current IQ ENABLE = Logic Low 4 8 mA
Limits
0 to 70C
Symbol
2.9 V VDD 13.2 V HI/LO = GND, RBIAS = 12.5 k LBOOST = 100 H, CBOOST = 100 nF
Mina
Typb
Maxa
Unit
Logic
Enable Turn-On Voltage Enable Turn-Off Voltage Enable Source Current Turn-On Time Turn-Off Time Turn-On Boost tOFF Initial Short Circuit tOFF Short Circuit Status Output Voltage Status Output Delay Time Status Threshold HI/LO Turn-On Voltage HI/LO Turn-Off Voltage VEN(on) VEN(off) IENSRC tON tOFF tON(BST) tOFF(ISC) tOFF(SC) VSTAT tSTDLY VSTATTHR VHILO(on) VHILO(off) VENABLE = 0V See Figure 3. See Figure 4. CGATE = 33 nF, See Figure 6. CGATE = 33 nF, See Figure 7. ISINK = 200 A See Figure 8. 0.85 x VDD 0.7 x VDD 0.3 x VDD 0.95 x VDD V 0.7 x VDD 40 120 5 5 600 10 2 0.4 V s s 0.3 x VDD V A
Gate Drive
Enhancement Voltage (VGATE - VSENSE) Source Current Sink Current VGS ISOURCE ISINK VCBOOST = 9 V 8.5 1.06 1.6 10.5 1.30 2.6 15 1.54 3.7 V mA
S-60752--Rev. C, 05-Apr-99 2
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SI9750
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Current Sense Circuit
Current Sense Amplifier Common Mode Range Current Sense Amplifier Voltage Offset Current Sense Amplifier Bias Current RLIMSET Reference Current Current Sense Amplifier Hysteresis Current Sense Amplifier Series Offset VCMR VOS ISOS IRLIMSET VHYST VSOS HI/LO = VDD, VCMR > 0.5 V Normal Operation 18 0 -3 -0.2 19.5 12 mV 20 21 VDD + 0.3 3 V mV
Limits
0 to 70C
Symbol
2.9 V VDD 13.2 V HI/LO = GND, RBIAS = 12.5 k LBOOST = 100 H, CBOOST = 100 nF
Mina
Typb
Maxa
Unit
A
Power On Reset
RESET Output Voltage RESET Output Hysteresisc RESET Comparator Input Threshold RESET Comparator Offset Voltaged RESET Comparator Input Bias Current RESET Timer Delay RETRY Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test. c. In a practical situation, VHYST is multiplied by ratio of a resistor divider chain. For VDD = 13.2 V, VHYST = 20 mV. d. The RESET comparator input threshold specification (VRST) includes the RESET comparator offset voltage. VOP(rst) VHYST VRST VRBIAS IBIAS tRSTD tRETRY CRST = 15 nF, See Figure 8. CRETRY = 100 nF 110 70 See Note c 1.223 IOUT = 1 mA, VDD > 2 V 2 1.250 0.5 -0.2 150 130 190 200 1.277 0.4 V mV V mV A s ms
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S-60752--Rev. C, 05-Apr-99 3
SI9750
Vishay Siliconix
PIN CONFIGURATION
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Function
BOOST VDD GATE LOAD SENSE LIMSET HI/LO ENABLE RBIAS VRST STATUS RESET CRETRY CRST GND COIL
Description
Output of on-chip Boost converter. A 100-nF capacitor should be connected between BOOST and GND Positive supply pin. Connection to external power MOSFET gate. Connection to positive supply side of LOAD. Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor. Connects overcurrent limit set resistor RLIMSET to the reference input of overcurrent trip comparator. CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND for low Capacitive loads and to VDD for high capacitive loads. CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high. A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator resistor RLIMSET and the GATE(on) charge current. See Functional Description for equations. Input to voltage monitor comparator. Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than 90% of VDD. Open drain NMOS output. This pin is driven low during power on reset or when VRST is lower than the internal 1.25-V reference. A capacitor connected from this pin to GND programs the retry timer. A capacitor connected from this pin to GND programs the reset timer. Negative supply pin. Connection to Boost converter inductor.
S-60752--Rev. C, 05-Apr-99 4
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SI9750
Vishay Siliconix
FUNCTIONAL DESCRIPTION
The SI9750 together with an n-channel MOSFET provides the following functions: * limits di/dt current for hot insertion applications * provides complete short circuit protection * high-side drive allows n-channel MOSFET to be used, for lower power dissipation * industry-standard microprocessor reset function * logic control input and outputs Setting the Current Limit (SENSE, HI/LO pins, RLIMSET, RSENSE) The current limit point is determined by the voltage across RSENSE, the value of RLIMSET, and the bias current. The current limit circuit is shown in Figure 1. The steady state current is set by the equation:
I LOAD x R SENSE > I BIAS x R LIMSET (1)
If a higher current limit is needed at start-up, the HI/LO pin can be tied high. The equation becomes:
I LOAD x R SENSE > 1.2 x I BIAS x R LIMSET + I BIAS ( 1k + R HI ) (3) ( HI/LO=High )
Notice that any current limit can be set at turn-on using an optional resistor, RHI. Relaxation Mode Current Limit (CRETRY pin) In an overload condition, the SI9750 will go into a relaxation mode current limit operation that not only protects the source and load, but also reduces the power dissipated in the MOSFET. When an overload is detected, the circuit quickly turns off, then goes into a retry mode whereby the current is ramped up slowly. If the fault still exists, the current will ramp down again. This sequence will repeat indefinitely at a period defined by 106 x CRETRY until the fault is removed. Typically, capacitors in the range of 1 nF to 1 F can be used on CRETRY, but the period should be >50 ms.
Due to the highly capacitive nature of some loads, the SI9750 has an option to increase the current limit point to a much higher level at turn-on. In this case, turn-on is defined as VGATE < VDD + 7.8 V. This function is implemented with the HI/ LO pin. If the HI/LO pin is tied low the current limit is 20% higher during turn-on than the steady state current limit point.
I LOAD x R SENSE > 1.2 x I BIAS x R LIMSET ( with pin HI/LO=Low ) (2)
FIGURE 1.
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SI9750
Vishay Siliconix
di/dt Limiting On Hot and Cold Insertion (GATE pin) The GATE pin provides a constant current source that is used to control the rate of rise of the gate of the MOSFET, and hence to control the di/dt of the load and source current. The equation that governs the gate current is:
12 I SOURCE = 1.25V x --------------- = 12mA R BIAS ( for R BIAS = 12.5k ) (4)
Logic Control (STATUS, ENABLE, RESET, VRST and CRST pins) STATUS. The status monitor detects when the load voltage is 90% of input voltage, VLOAD > 0.9 x VDD. This pin is an opendrain NMOS output, capable of sinking 200 A at VOL = 0.4 V. If this pin is used in conjunction with the ENABLE of another unit, power supply sequencing (or daisy-chaining) is easily implemented. ENABLE. This CMOS logic compatible input serves as the on/off control pin. This pin has 40-A minimum pull-up to VDD. RESET (VRST, CRST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on VRST pin and compares it with 1.25 V. This function is programmable by using an external voltage divider. When VRST is higher than 1.25 V, the reset signal is delayed by the CRST pin, defined by Equation (6) and then goes high (Figure 8).
Reset delay t RSTD 10 x C RST
4
Typically, a 33-nF capacitor should be connected from the GATE pin to ground. If a large ISOURCE is needed for high di/ dt, a 330- resistor in series with CGATE may be necessary to prevent oscillation. In the case that VDD > 6 V, a resistor of approximately 330 is also recommended in series with the gate (Figure 1). Reference Bias Current (RBIAS pin) This pin sets the internal current used by RLIMSET to determine all the current limit points. Typically RBIAS = 12.5 k which sets a 20-A bias current. The equation which relates RBIAS to IBIAS is:
1.25V I BIAS = ------------------------ = 20A 5 x R BIAS ( for R BIAS = 12.5k ) (5)
(6)
Power on Reset (POR) (VDD pin) This function monitors the voltage on the VDD pin and signals the system if all input voltage requirements have been met. At turn-on when VDD > 2.7 V " 200 mV, a POR signal is generated for a duration of 100 s. After this point the system is released into operation. If VDD falls below 2.7 V " 200 mV, a second POR signal will be generated. If two POR signals are detected, this indicates that the source for VDD is not capable of supplying the load current. The IC then turns off the MOSFET and initiates its retry period, hence fully protecting the MOSFET from an over-power condition. Boost Converter (COIL, BOOST pins) The boost converter generates the gate drive for the external n-channel MOSFET. This is limited to typically VDD + 11 V. The boost inductor should typically be 100 H, <3.5 , >180 mA dc, and the boost capacitor should be 100 nF. FIGURE 2. Typical Operation Under Start-up Condition with an Overcurrent Fault Applied to the Output
S-60752--Rev. C, 05-Apr-99 6
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SI9750
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS NOTED)
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SI9750
Vishay Siliconix
SWITCHING TIME TEST CIRCUITS
FIGURE 3. Normal-Mode Operation
FIGURE 4. Timing Definition with ENABLE Already On
FIGURE 5. Start of Boost Converter
S-60752--Rev. C, 05-Apr-99 8
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SI9750
Vishay Siliconix
FIGURE 6. First Short Circuit
FIGURE 7. Relaxation-Mode Current Limit
SWITCHING TIME TEST CIRCUITS
FIGURE 8. STATUS and RESET
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